Analyzing the Impact of Approximate Adders on the Reliability of FPGA Accelerators

In this paper, we evaluate the impact of approximate adders on the reliability of FPGA-based accelerators for applications that present inherent error resilience. We perform an exhaustive fault injection campaign to examine the effects of single bit upsets (SEUs) in the adders in the DCT block of a JPEG encoder IP core. We analyse how much the reliability of the JPEG encoder deteriorates with the use of approximate instead of accurate adders.