Applying IEEE Std 1838 to the 3DIC Design Trishul – A Case Study

New ways of addressing performance power and area are required as Moore’s Law reaches its limits. One such way is stacking die within a package, also known as 3DIC. A method to deliver test stimulus and observe test results to each die in the stack is required to enable manufacturing test of the 3DIC. IEEE Std 1838 defines a standardized methodology for testing stacked die. A testchip, Trishul, was created to enable evaluation of EDA tool and fab capabilities when creating a high-density logic 3DIC. It includes a synchronous cache coherent mesh interconnect design which could operate at frequencies up to 2.4GHz. It uses 5.76 µm pitch face-to-face wafer bond connections on 12nm FinFET technology. This testchip also includes the first known industry demonstration of IEEE Std 1838 which enabled each die to be tested as well as enabling die-to-die testing.