The Effect of Instruction Format on the CPU Performance

Many computer systems benefit from fault tolerance by the ability to continue normal operation in spite of the presence of faults. Safety and critical areas that lead to financial or human life losses such as emergence dispatch, nuclear reactors control and others require continuity of services and proper operations. Fault tolerance techniques are necessary in order to minimize the probability of catastrophic failures and to increase system reliability and availability. In this paper a fault tolerant technique is proposed that adds an extra bit in the instruction format of the CPU to distinguish between an opcode and data to tolerate control flow faults. The proposed solution is designed at the register level and tested by simulation. A set of different faults were injected in a microprocessor system. Error coverage and latency are analyzed to highlight the capability of the proposed technique.