A High Throughput QC-LDPC Decoder Architecture for Near-Earth Satellite Communication

This paper presents a high throughput decoder architecture for the (8176,7154) quasi-cyclic (QC) low density parity check (LDPC) code (C2) recommended by the Consultative Committee for Space Data Systems (CCSDS) for near-earth applications. The architecture avoids memory conflict through the use of multiple shift register based memory circuits and a pipe stage forwarding mechanism, thus allowing for heavy pipelining of the core processing unit. The decoder is implemented on the Xilinx XCVU9P FPGA platform and achieves a throughput of 2.65 Gbps at 10 iterations at a clock frequency of 253 MHz.