Hardware Implementation of a Latency-Reduced Sphere Decoder With SORN Preprocessing

Unum type-II based Sets-Of-Real-Numbers (SORN) arithmetic is a recently proposed, promising number representation providing fast and low complex implementations of arithmetic operations at the expense of low resolution. The format can be applied for constraining large optimization problems by means of preprocessing. In this work SORN arithmetic is applied for reducing the latency of a Sphere Decoder by excluding a number of solutions in advance. In particular, a comprehensive hardware implementation is presented, consisting of an adapted Sphere Decoder, as well as SORN and matrix preprocessing. Logic and physical synthesis evaluations show that the mean number of visited nodes within the Sphere Decoder can be reduced by up to 76%, resulting in an overall latency reduction of up to 20%. This improvement comes with an area and energy increase of up to 58% and 83%, respectively, compared to a standard Schnorr-Euchner Sphere Decoder.