Sensitivity Analysis and Design of Negative-Capacitance Junctionless Transistor for High-Performance Applications

In this work, we perform the sensitivity analysis of negative-capacitance (NC) junctionless (JL) transistors considering the variation in device parameters and compared its performance with conventional JL devices. The OFF-current ( I
_OFF
) of the JL transistor degrades significantly as the film thickness ( T
_si
), channel doping ( N
_ch
), and oxide thickness ( T
_ox
) increase and the gate length ( L
_g
) decreases. However, compared to JL devices, I
_OFF
degradation due to increasing T
_si
and N
_ch
and decreasing L
_g
can be effectively mitigated in NCJL devices. The reduced I
_OFF
and lower I
_OFF
sensitivities in the NCJL transistor are due to the occurrence of more negative internal gate voltage at higher T
_si
and N
_ch
and lower L
_g
, which enhances the channel depletion and reduces the I
_OFF
sensitivity. The impact of T
_ox
and the spacer permittivity ( ε
_s
) shows that reducing T
_ox
and increasing ε
_s
significantly improve the ON-current in NCJL devices due to better capacitance matching at the ON-state. Besides, for the first time, a design methodology is proposed to optimize the NCJL device for high-performance (HP) applications at L
_g
= 15 nm. The results presented in this article serve as a guideline to extend the usability of NCJL devices for HP applications.