A Compact, Low-Phase Noise Fractional-N PLL for Global Navigation Receiver

This paper presents a compact, low-phase noise fractional-N phase-locked loop (PLL) for navigation receivers operating in the frequency bands L1, L2, L5, and S (1.1-2.5 GHz). The PLL supports multi-standard navigation receivers for IRNSS, GPS, Galileo, Beidou, and GLONASS. A new PLL architecture using a single LC voltage controlled-oscillator (VCO) is proposed for multiband operation compared to the state of the art receivers using multiple VCOs or PLLs for the multi-band operation. A 3
^rd
order 1-bit Delta-Sigma Modulator (DSM) is used for fractional frequency division. The PLL achieves the best phase noise of -116.2 dBc/Hz at 1 MHz offset in the L5 band. The PLL is integrated into a multi-standard navigation receiver, fabricated in 65 nm CMOS technology. The PLL consumes a power of 15.7 mW from a 1.2 V supply and occupies an area of 0.25 mm
²
in the complete receiver.