FDSOI Sip Epitaxy Optimization for Leakage Reducing

As short channel effect turns into a major constraint for traditional bulk silicon devices when CMOS technology scales down to 22nm and beyond, fully depleted silicon on insulator (FDSOI) devices becomes more popular in integrated circuit manufacture. Selective Si:P epitaxy is novelly applied for FDSOI NMOSFET as raised source and drain to enhance drive current by increasing channel electron mobility and reducing contact resistivity. However, the off-state leakage current (Ioff) increased with in-situ-Phosphorus-doping epitaxy, where source/drain Phosphorus lateral diffusion to channel is suspected to impact NMOS leakage. In this paper, an optimized dual-layer Si:P epitaxy process is proposed to reduce leakage, thereby boosting the NMOS device performance.