Etch Back Before ILD-CMP for Improving the Loading Issue after ILD-CMP

Inter-level dielectric chemical mechanical polishing (ILD CMP) technology has become one of the crucial technologies in integrated circuit which can contribute to the subsequent interconnections of metal and lithography processes. There is a step height between the gate scribe line and dense line which because of the gate and the higher gate is, the bigger step height is. The loading issue will not suffer after ILD CMP when the step height is within a certain range [1]. However, the gate must be very high or even twice as much due to process performance needs in 38 supper flash. In this situation, there will be a serious loading issue after ILD CMP. This paper will present how to improve loading with both etch-back and ILD CMP. Experiment results shown that there is no loading after ILD CMP when add etch-back process before ILD CMP.