Impact of the Stress on Reference Voltage of Power SIP Chip Applied in 5G Based Station

The reliability problem of domestic self-developed chips restricts the wide application of electronic products. Most reliability problems are caused by stress, including residual stress before and after encapsulation and stress introduced during the reliability test. For power chip, the stress is the main cause of the drift of reference voltage test values or failure. In this paper, the effect of different factors of stress source on the reference voltage after temperature cycling test is analyzed through the encapsulation material, die thickness and design of key parameters of temperature cycling test, based on issues of reference voltage failure in the reliability process of power SIP chip, combined with the JEDEC standard.