A Configurable Computing-in-Memory Structure Based on Convolutional Neural Network

This paper addresses the power consumption of the data movement of the Von Neumann architecture via a SRAM-based computing-in-memory (CIM) architecture. Three IOT SRAM arrays (3×128×256=96K) are fulfilled to support configuration as multi-bit 2-D convolution kernels or 1-bit 3-D convolution kernel to adapt to the different convolutional neural networks (CNN). Simulation in a standard 14-nm CMOS process, the proposed CIM system achieves good performance and energy efficiency for pattern recognition. The 2D 8-bit weight convolution power efficiency in inference phase can reach 6.27 TOPS/Wand the 3-D convolution power efficiency in inference phase can reach 17.29 TOPS/W.