Research on the Improvement of SI Performance of High Bandwidth Memory Interface by New 2.5D Silicon Interposer Structure

With the rise of AI, big data, 5G and other services, high bandwidth, low power consumption, and low latency have become the basic characteristics of the new generation of chip technology. HBM(High Bandwidth Memory) technology has become the first choice for high-end memory chips due to its ultra-high bandwidth and short-range chip interconnection. The HBM interface has now been developed to HBM2E, the signal rate has reached 3600Mbps, and HBM3 will also be available soon. The high speed and high density interconnection between dies has brought serious signal integrity (SI) problems. The traditional 2.5D silicon interposer process can no longer meet the application of HBM2E products. This article focuses on the establishment of the 2.5D silicon interposer SI simulation analysis process, and try to find the solutions to the SI issues of HBM2E and even HBM3 high-speed parallel interfaces.