Inferring Custom Synthesizable Kernel for Generation of Coprocessors with Out-of-Order Execution

The research is devoted to the problem of project- specific steep learning curve when designing complex hardware microarchitectures. To address this issue, it is proposed to use custom synthesizable kernels that provide computational model inferred from specific properties of target microarchitectures. Using ActiveCore hardware generation framework, previously developed by the author, inference of such kernel for coprocessors with out-of-order (OoO) execution and register renaming is demonstrated. Hardware generator packaged with this kernel offers behavioral specification of execution pipelines functionality and provides decoupled latency-insensitive interface for execution units, which allows to generate designs both in RTL and HLS form in arbitrary combinations. Experimental OoO FPU coprocessor based on this kernel shows capability for concise, high-level, untimed specification, while having sufficient performance for integration with superscalar OoO CPU designs.