Importing Custom DNN Models on FPGAs

With the recent advances and the proliferation of low-power and resource constraint embedded hardware being deployed in the field, the edge computing paradigm has become more prominent. Nowadays, it is possible to apply Machine Learning (ML) algorithms and Deep learning (DL) architectures, like Deep Neural Networks (DNNs), by exploiting these edge devices. There is also a plethora of software frameworks to transform the typically complex computations and accommodate the implementation process and specifically for those who are targeted to field-programmable gate arrays (FPGAs), quite a few challenges need to be addressed. Therefore, there is an active research development towards providing efficient techniques for applying DNNs models to these devices. In this paper, we propose a methodology which combines two research tools for the generation of a register-transfer Level (RTL) design using a hardware description language (HDL). We evaluate different implementations experimenting with a set of DNN models in different FPGA boards.