FPGA Implementation of FIR Filter Architecture using MCM Technology with Pipelining

The transpose form of (FIR) is a pipeline structure that supports the MCM (Multiple Constant Multiplication) technology, but the direct form of the FIR filter shape is not compatible with the MCM technique. MCM is most effective for the transpose form when the overall operation is greater than the regular additions that reduce computation delays. In this paper, efficient Pipeline based FIR filter with MCM designed was implemented using Verilog HDL, simulated, synthesized in Xilinx ISE tool, and implemented on ARTIX-7 FPGA board. Results shows that area, delay and computational complexity reduced for MCM based FIR filter with pipeline comparative to without pipeline.