A Comparative Analysis of Domino Techniques for Improved Performance

In this paper, for the first time, we have performed comparative analysis of different styles of domino circuits, based on average power consumption, unity noise margin (UNM) and number of transistors associated with them under same delay i.e., 120ps (iso-delay). The domino logic circuits which have been compared are conventional domino with and without evaluation transistor, diode footed domino (DFD), voltage comparison domino (VCD), low power Domino (LPD), controlled keeper by current comparison domino (CKCCD) and, high-speed domino (HSD). Simulations performed for S-bit OR gate using a 180nm CMOS technology model at an operational temperature of 110°C and supply voltage of l.8V in Cadence Virtuoso tool. Results are compared with conventional domino with evaluation transistor. It has been found that low power domino (LPD) gives the best results considering all three performance parameters, in terms of 93.6% power reduction and 1.317x improvement in noise immunity.