Influence of High-k Dielectrics on Nanowire FETs

In this work, design optimization of Nanowire Field Effect Transistor (FET) has been carried out for switching applications. The reported device offers an increase of 122 μA in drive current as compared to the device with SiO
₂
as a gate oxide and I
_on
/I
_off
ratio of 10
⁷
. The threshold voltage (V
_th
) is 0.35V with Drain Induced Barrier Lowering (DIBL) of 60.52 mV/V and Subthreshold Swing (SS) of 72.04 mV/Dec. The off-state leakage (I
_off
) is 103.75 pA which is 71.67 pA higher than SiO
₂
based device but can be traded-off with an increased drive current of 161 μA and transconductance of 642.78 μS in HfO
₂
based device making it suitable for digital logic applications.