An Area Efficient VLSI Architecture for 1-D and 2-D Discrete Wavelet Transform (DWT) and Inverse Discrete Wavelet Transform (IDWT)

Several discrete wavelet transform architectures have already been introduced due to their wide range of applications in the field of image, video and speech signal processing. In this paper, an area efficient VLSI architecture for 2-dimensional discrete wavelet transform (DWT) and inverse discrete wavelet transform (IDWT) have been proposed. Theoretically, the hardware and timing analysis of existing and proposed architectures are presented. The proposed and existing several architectures are also simulated and synthesized for virtex-4 FPGA device. Performances of all architectures are observed in terms of slice, slice flip-flops, clock frequency using Xilinx ISE Design Suite 14.7 Synthesis tool. Also the number of slice LUTs, slice registers, clock frequency, delay and power of proposed DWT and IDWT architectures are found using virtex-7 FPGA device family.