A 0.6 V 1.6 nA Constant Current Reference Circuit with Improved Power Supply Sensitivity

This paper presents a low power current reference circuit with improved power supply sensitivity. The proposed circuit is designed in SCL 180 nm CMOS technology and simulated using Cadence Virtuoso. It generates a reference current (Iref) of 1.6 nA at 0.6 V supply voltage (Vdd) at room temperature (27° C) with a total power consumption of 10 nW (0.6 V). A new circuit configuration based on composite transistor operating in weak inversion has been proposed in this work. The proposed circuit is an improvisation on beta-multiplier circuits proposed earlier. The circuit improves the power supply sensitivity of the current source and provides a better performance in terms of process variability.