Minimizing Wirelength with Bend Reduction using Gradient Descent PSO Hybrid in VLSI Global Routing

Contemporary evolution in assembling billions of transistors in a solitary bite of VLSI chip and additionally the decrease in the dimension of chip from micrometer to nanometer level demonstrates increased complexity where VLSI global routing play the crucial role in reducing delay and power loss. The objective of minimizing overall wirelength of interconnected nodes formulated as Rectilinear Steiner Minimal Tree (RSMT), a NP-complete problem and subsequent bend reduction increases the possibility of via minimization in the later stage of VLSI physical design thereby achieving less power loss and less interconnect delay. Notable computational approaches had been tried out by researchers but finds limitation for higher dimensional layout. In lieu of overcoming increased complexity metaheuristic algorithms like basic Particle Swarm Optimization (PSO), Genetic Algorithm (GA), Ant Colony Optimization (ACO) and their hybrids have already found their fruitful application for this purpose but sometimes with the limitation of divergence. This paper proposed a hybrid of Gradient Descent algorithm along with Particle Swarm Optimization (PSO) thus yielding an evolutionary hybridized optimization approach (GDPSO) which is implemented for discovering the RSMT followed by reducing the bend quantity. Moreover the proposed algorithm is compared and analyzed with the existing metaheuristic approach and Geosteiner benchmark to establish its more effectiveness in VLSI routing paradigm.