Radiation-Hardened Low Read Delay 12T-SRAM Cell for Space Applications

This paper proposes a Radiation-Hardened Low Read Delay improved 12-Transistor (RHLRD-12T) SRAM cell. By circuit optimization technique in 16-nm CMOS technology, the simulation results show that the proposed circuit can recover from single-event upset (SEU). It can also recover from single-event-multiple-node upset (SEMNU) that is induced due to the charge sharing among OFF-transistors. The proposed RHLRD-12T SRAM cell exhibits 1.34× (1.03×) longer (shorter) Write Access Time compared to RHBD-12T (RHBD-10T). It shows 1.2× (1.13×) improvement in Read Access Time compared to RHBD-12T (RHBD-10T). It exhibits 1.06× (1.32×) higher (lower) CWLM compared to RHBD-10T (RHBD-12T) SRAM cell.