Synthesis of low-leakage PD-SOI circuits with body-biasing

In this work we propose a methodology for the reduction of leakage power dissipation through the use of smart body contacts in a partially depleted Silicon-on-Insulator (PD-SOI) technology. Reverse body biasing is used to increase threshold voltage in standby while in active mode PD-SOI gates switch with nominal Vth. As opposed to standard dual-Vth techniques used in CMOS bulk circuits, PD-SOI enables the application of body-bias to all gates included those in critical paths without delay penalties. Results are reported for the ISCAS85 combinational benchmarks.