A sub-1V dual-threshold domino circuit using product-of-sum logic

A sub-1 V dual-threshold domino circuit is proposed to accelerate the operation of CMOS digital circuits at below 1 V. The circuit combines a low and high threshold-voltage (Vt) MOSFET with standby control to make it possible to achieve high-speed evaluation and low standby leakage current. A low-Vt foot nMOSFET is used to shorten precharge time and increase throughput. A product-of-sum logic form is used for implementation of a pull-down logic to increase the noise margin. An experimental 64-bit carry look-ahead (CLA) adder demonstrated a 0.6 V operation with a standby power of 0.4 /spl mu/W and a delay time of 4.8 ns.