Scaling of stack effect and its application for leakage reduction

Technology scaling demands a decrease in both V/sub dd/ and V/sub t/ to sustain historical delay reduction, while restraining active power dissipation. Scaling of V/sub t/ however leads to substantial increase in the sub-threshold leakage power and is expected to become a considerable constituent of the total dissipated power. It has been observed that the stacking of two off devices has smaller leakage current than one off device. In this paper we present a model that predicts the scaling nature of this leakage reduction effect. Device measurements are presented to prove the model's accuracy. Use of stack effect for leakage reduction and other implications of this effect are discussed.