A low-leakage dynamic multi-ported register file in 0.13 /spl mu/m CMOS

Increasing leakage currents combined with reduced noise margins are seriously degrading the robustness of dynamic circuits. This paper describes a dynamic implementation of a 256/spl times/32b 4-read/write-port register-file for /spl sim/6 GHz operation at 1.2 V in a 0.13 /spl mu/m technology. The pre-charged local bit-lines utilize an efficient conditional keeper-technique, where a large fraction of the keeper is turned ON only if the dynamic output remains high in the evaluation phase. Using this technique, we are able to improve upon all-low-Vt performance by 4%, while maintaining dual-Vt usage. Thus, the robustness is improved by 96% and the active leakage power is reduced by 5/spl times/.