A Dual-Entropy-Superposed PUF With In-Cell Entropy Sign-Based Stabilization

In this paper, we present a novel physical unclonable function (PUF) based on dual entropy sources of a 2-transistor voltage reference (2T-VR) and a four-stage diode-clamped comparator. Featuring excellent stability over wide range of supply voltage and temperature, the proposed 2T-VR is constructed with one native transistor plus one PMOS transistor that are compensated to minimize its temperature coefficient. Moreover, different from most previous PUF implementations where a digital comparator with offset-cancellation is needed for digitizing the mismatched voltages/currents from the prior entropy stage, in this work, the customized diode-clamped comparator’s offset is well-exploited as an additional entropy source, which can be superposed on the above 2T-VR-based entropy to significantly elevate the whole PUF structure’s reliability. Besides, a near zero-overhead in-cell entropy sign based stabilization (ESS) scheme is proposed to further enhance the reliability by stabilizing the scenario with the dual entropy sources having opposite signs. The designed dual-entropy-superposed PUF is fabricated using a 65-nm standard CMOS process, and its excellent randomness is validated using the widely-accepted National Institute of Standards and Technology (NIST) PUB 800-22/800-90B and autocorrelation function (ACF) test tools. With the test chips repeatedly challenged at normal condition up to 4000 times, the measured native bit error rate (BER) and unstable bits are reported to be 0.16% and 1.3%, respectively. Moreover, with the operating temperature changing from −50°C to 130°C and the supply voltage changing from 0.8 V to 1.4 V, the native BER’s VT sensitivities without stabilization are measured to be 0.195%/10°C and 0.651%/0.1 V, respectively, which can be further reduced by
$4.5\times $
and
$1.5\times $
with the proposed ESS scheme applied.