Improving the specific on-resistance and short-circuit ruggedness tradeoff of 1.2-kV-class SBD-embedded SiC MOSFETs through cell pitch reduction and internal resistance optimization

The impact of cell size and JFET width reduction on static and dynamic device characteristics is investigated in 1.2-kV-class Schottky barrier diode (SBD)-embedded SiC metal-oxide-semiconductor field effect transistors (MOSFETs). We compare a conventional SBD-embedded MOSFET with improved SBD-embedded MOSFETs with smaller cell pitch and JFET width than the conventional SBD-embedded SiC MOSFET. The optimized SBD-embedded SiC MOSFETs achieve 39% lower on-resistance and 16% lower switching energy loss compared with the conventional design. We also investigate the tradeoff between R
_on
A and short-circuit withstand time (t
_SC
). Although R
_on
A reduction generally causes a decrease in short circuit withstand capability and reverse conduction capability, we demonstrate that the optimized SBD-embedded SiC MOSFETs have a lower forward voltage drop and short circuit withstand capability. These results show that it is possible to simultaneously reduce R
_on
A and improve t
_SC
with adequate optimization.