Study of Unique ESD Tolerance Dependence on Backgate Ratio for RESURF LDMOS with Rated Voltage Variation

This paper describes that an unique ESD tolerance dependence on a backgate ratio of fully isolated RESURF LDMOS for various cases of rated voltage. For the LDMOS of rated voltage below 60V, the ESD tolerance increases as the backgate ratio increases, which is well-known method to achieve the highly-ESD tolerant devices though scarifying the on-resistance. However, the LDMOS of rated voltage above 80V shows no dependence on the backgate ratio. The mechanism of this phenomenon has been investigated utilizing 2D TCAD simulation and found that the electrical potential of a floating N+buried layer contributes to parasitic bipolar action during ESD events and determines the ESD tolerance. The LDMOS design has to be carefully performed with considering this unique ESD tolerance dependence on the backgate ratio.