Surge current capability evaluation of 6.5kV SiC MOSFETs with 3D cell layouts

This paper presents for the first time a combined experimental/numerical study of the electro-thermal surge current behaviour of 6.5kV SiC MOSFETs for various cell layouts. By means of a matched TCAD model it is demonstrated that the circular (and hence also the hexagonal) topology shows an inferior surge capability to the stripe. Conversely, the ALL allows for the dissipated losses and the peak lattice temperature attained during a 10ms pulse test to be reduced in both body and channel diode mode. In this context, it is shown that the sensitivity of the device's response to the active area can be decreased at smaller pitches.