Design and comparative analysis of dynamic threshold MOSFET and sleep transistor configuration based 7T SRAM cell

Static Random-Access Memory cell is one of the main data storing element in the memory which also occupies a major portion in memory unit. Various topologies and modifications have been proposed to improve the propagation delay and power dissipation for SRAM cells. This paper proposes a design and performance analysis of a 7T SRAM using four different design techniques namely DTMOS, sleep transistors, and conventional MOSFET. The circuits have been simulated at 90 nm PTM technology node in LTSpiceXVII Software. All the circuit operates at supply voltage (Vdd) of 300 mV. Comparative analysis in between all the simulated designs and reported work has been done and is based on technology node, power dissipation, and propagation delay. Power delay product and Energy delay product has been found for all four techniques. The output graph has been displayed which show the transient analysis of SRAM cell i.e., the change in waveform with relation to time. The comparative simulation results infer that combination of DTMOS and sleep transistor technique for design of 7T SRAM cell showed 83% reduction in power dissipation whereas design of 7T SRAM using sleep transistor design technique showed 12% enhancement in propagation delay when compared with conventional MOSFET 7T SRAM.