A 50-MHz SAR ADC-Based fS/4 Noise-Shaping Bandpass ADC

A f
_s
/4 band-pass ΣΔ-analog-to-digital converter (ADC) architecture is realized by feeding back the delayed quantization noise produced by a successive approximation register(SAR) ADC. Designed in a SMIC 180nm CMOS process, the ADC sampling at 50 MHz achieves Signal-to-Noise-Ratio(SNR) of 80.85 dB in a 0.78125 MHz bandwidth when the Over-sampling Rate(OSR) is 32. For a 8-bit SAR ADC, Effective Numbers of Bits (ENOB) is improved 2.6 bits with the band-pass noise shaping.