Anomalous GIDL Effect With Back Bias in FinFET: Physical Insights and Compact Modeling

In this work, we report a detailed study and modeling of bulk current in the low forward bias region. In the forward bias region, the bulk current shows a gate-induced drain leakage (GIDL) such as strong modulation with gate voltage although from the band alignment one would not expect any tunneling current. We propose physics-based modeling of this effect and derive a compact model for circuit simulators as state-of-the-art compact models are not suitable to capture this effect. The proposed model has been validated with measurement from Intel's bulk FinFET device.