A High Speed NTT Accelerator for Lattice-Based Cryptography

As the most computing-intensive operation in lattice-based cryptography, polynomial multiplication is the bottleneck for high speed and low-latency implementation of these schemes. In this paper, a vector number theoretic transform (NTT) accelerator is proposed to speed up this process. First, an efficient addressing scheme for the vectorized NTT/INTT is proposed to achieve a conflict free situation and make full use of hardware resources. Then, a flexible architecture is presented with a series of timing and low-power optimizations. Finally, the accelerator is implemented using TSMC 28nm technology. Approximately, 274k equivalent gates and 10kB SRAM is consumed by the proposed accelerator and 47.5ns is only needed to complete a 256-point NTT. Experimental results show that the energy-efficiency and processing speed achieves more than 17.6× and 3× improvements with 50% area saving than the state-of-the-art design.