Hardware Implementation of Fixed-Point Decoder for Low-Density Lattice Codes

In this paper, a fixed-point arithmetic low-density lattice code (LDLC) decoder is designed and implemented on an FPGA where Gaussian mixture messages that are exchanged during the iterative decoding process are approximated to a single Gaussian. Numerical simulations are performed to find the minimum number of bits required for the fixed-point decoder implementation to attain a frame-error-rate (FER) performance similar to a floating-point LDLC decoder implemented in C. This is found to be 12 integer bits, 8 fractional bits and a sign bit. Efficient methods are used to numerically approximate the required non-linear functions such as division and exponentiation. A two-node serial LDLC decoder implemented on an Arria 10 FPGA is presented as a hardware proof-of-concept that attains a throughput of 440 Ksymbols/sec at high signal-to-noise ratio (SNR). This throughput is obtained at clock frequency of 125MHz and for a block length of 1000. The throughput is further improved with a partially-parallel architecture that achieves a throughput of 5.75 Msymbols/sec at high SNR.