RF Performance of Devices Processed in Low-Temperature Sequential Integration

RF performance and intertier coupling of CMOS processed in 3-D sequential integration are investigated. pMOS transistor fabricated with a 500 °C thermal budget features good RF figures of merit with
${f}_{t} =105$
GHz and
${f}_{\text {max}} =175$
GHz for a gate length of 45 nm and
${V}_{\text {DD}} = -1$
V. Moreover, we demonstrate that the low-
${k}$
SiCO oxide spacer and low polysilicon gate resistance obtained with the low temperature process contribute to
${f}_{\text {max}}$
results that are better than high temperature process (above 1000°). Finally, we illustrate the crosstalk effects and the influence of the low-tier transistor gate voltage
${V}_{\text {G}}$
on the top-tier threshold voltage
${V}_{T}$
. We also show that a polysilicon ground shield integrated under the top-tier transistor substantially attenuates the intertier RF field coupling effects.