Simulated Annealing Algorithm & ReRAM Device Co-optimization for Computation-in-Memory

This paper co-optimizes simulated annealing (SA) algorithm and 40 nm TaO
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-based resistive random access memory (ReRAM) for computation-in-memory (CiM) to solve combinatorial optimization problems such as the knapsack problem. SA in ReRAM CiM promises low power consumption, high throughput, and high scalability. However, in ReRAM, bit-error occurs and ‘Current window’ becomes small. First, to overcome ReRAM device problems under high stress condition, Adaptive Endurance Relaxation (AER) is proposed to adaptively change the interval of relaxation based on Set/Reset cycles. By applying AER to ReRAM, Bit-Error Rate (BER) decreases by 100% and the current window increases by 21.2%. Second, SA algorithm mapping to ReRAM-based CiM is proposed. SA algorithm mapping enables ReRAM CiM to calculate Hamiltonian, which is equivalent to Ising model. By combining two proposals, SA Algorithm and Device Co-optimization (ADCO) improves the acceptable bit precision by 2 bits and the acceptable BER twice.