A Time-Based Pipelined ADC Using Integrate-and-Fire Multiplying-DAC

This paper presents a new time-based pipelined analog-to-digital converter (ADC) with multiplying-DAC (MDAC) stages capable of robust 2 × residue amplification by subtracting two pulse widths. First, the input voltage is converted into two timing pulses containing the information of the time difference between their rising edges. Each MDAC stage performs 1.5-bit quantization and generates two turn-on pulses with pulse widths bearing the opposite signs of the residue, + T
_res
and -T
_res
. The following pair of integrate-and-fire circuits, each containing a current source charging a capacitor to a threshold voltage, computes the difference between the two pulse widths, T
_res
-(-T
_res
)=2T
_res
, and generates new timing pulses bearing the 2× amplified residue for the next stage. The circuit non-idealities in the MDACs contribute to the offset errors but not to the gain errors in their transfer curves, making the calibration simple. Moreover, the ADC does not require amplifiers, making it suitable for low-voltage digital processes. The prototype 10-bit pipelined ADC fabricated in 28-nm CMOS dissipates 1.55-mW at 125-MS/s and occupies 0.025 mm
²
. With signal-to-noise and distortion ratio of 44.3 dB and spurious-free dynamic range of 53 dB for a 1-MHz sinusoidal input, the ADC has a figure of merit of 96.8-fJ/conversion step.