The Design and Verification of the DART Single Board Computer FPGA

The NASA Double Asteroid Redirection Test (DART) is a technology demonstration mission to test the kinetic impactor technique on a binary near-Earth asteroid system, Didymos. Internal to the DART spacecraft is the Single Board Computer (SBC) card, - the main computing element of the spacecraft. The SBC contains the LEON3FT UT700 processor and the DART Single Board Computer FPGA. The DART SBC FPGA is a System on a Chip (SoC) design, supporting payload and bus-side functionality in a single chip. 10+ designers split into three teams worked on the FPGA: the avionics design team for the bus-side functionality, the image processing design team for the payload, and the FPGA System team for overseeing the FPGA top-level integration and verification. The DART SBC FPGA performs routing of the spacecraft communication and forwarding of timecodes, handles critical commands used to help recover the spacecraft, provides interrupts to the UT700 processor, provides boot management to the UT700, and provides a watchdog timer. The DART SBC FPGA is a key component of the spacecraft avionics and provides required functionality to flight software (FSW) running on the UT700. The DART SBC FPGA also receives image data from the instrument, performs image processing, transmits post-processed images back to Earth, and supports recording images to NAND Flash for later retrieval. More specifically, the FPGA consists of three key parts: SpaceWire modules for data communication and execution, support infrastructure for FSW, and onboard image processing. The FPGA contains the spacecraft's central Space Wire router with 9 SpaceWire ports that receives and transmits data traffic to their designated destinations. The FPGA also controls the boot loading of FSW and additionally provides FSW registers, a watchdog timer, general purpose timers, reads /writes to flash, reads/writes to MRAM, reads/writes to SRAM, GPIOs, test functions, and interrupts. The FPGA receives image data sent through a SERDES interface, performs image processing to support autonomous navigation, and finally sends the processed image out to the radio. The FPGA also executes ground-initiated commands independent of the FSW to support key configuration and critical recovery functions. The DART SBC FPGA was challenging to integrate and verify due to its complexity and large design. To guarantee the correctness of the SoC design, the team created new roles and a new methodology with multiple verification checks including an ©2021 IEEEautomated regression test in simulation. This paper describes 1) the requirements and architecture of the DART SBC FPGA design, 2) the design and verification methodology employed, 3) the challenges faced in designing the large and complex design on the Microsemi RTG4 FPGA, and 4) the results and lessons learned.