FPGA Implementation and Study of Synchronization of Modified Chua’s Circuit-Based Chaotic Oscillator for High-Speed Secure Communications

This paper presents an implementation of modified Chua's circuit-based chaos generator in a field-programmable gate array (FPGA) and explores the synchronization of such generators for use in secure communication systems. The chaos generator design employs a fixed-point numeric format and the Forward Euler differential equation numerical solution method. The implementation of chaotic generator on Intel Cyclone V FPGA demonstrates the stable generation of sampled chaotic signal with up to 76 MHz clock frequency. The correctness of the realization is verified using a comparative analysis of the Simulink functional model and FPGA implementation.