Poly CMP Process Challenges for Embedded Array Devices

Challenges in poly Chemical Mechanical Planarization (CMP) process are scalability in order to achieve low defects for embedded devices. In this paper, we demonstrated the poly CMP process characterization, including process recipe margin check with wafer thickness correlation studies, as well as active pitting and artifact defect improvement. This process is challenging as due to the challenge of thin poly in the embedded flash chip design, low dishing performance is preferred. Thus, Poly CMP process margin is evaluated to be robust, by collecting within-wafer poly thickness measurement of CMP monitoring structure as well as transmission electron microscope (TEM) analysis included. Next, defectivity improvement study had been carried out for poly CMP process. Chronic defect seen is surface roughness defect and overpolish pitting defect. These defects can be gradually reduced by implementing recipe optimization work. Optimum process characterization and robust window margin in poly CMP process can improve scalable embedded poly CMP devices.