Investigating the root cause of WAC Vt fliers and Control plan for RF FEM : Yield Enhancement

We investigated and resolved the problem of WAC (wafer acceptable criteria) FET threshold voltage (Vt) fliers in a 130nm technology. Our investigation shows that failed Vt sites on the test maps are due to the incomplete resist removal at boron well implant level (P2 level). Test maps showed strong correlation with subsequent photo defect inspection (PDI) steps. PDI inspections show resist residues of the prior level. We also noticed that the photolithography rework rate increased for the subsequent level. TEM analysis on the failed site confirmed the presence of resist residues, which blocked subsequent implants. We correlated the failed wafers to the P2 level resist removal tools. Our study showed that switching to and customizing a plasma strip tool with direct contact heated chamber improved the resist removal process. With these changes the WAC Vt fliers were removed.