Quick Yield Impact Assessment Using Silicon-design Correlation to Address Design Systematics

At sub 14nm technology nodes, the ability to design, verify, and manufacture integrated circuits (IC) with high yield gain has become a major challenge. With the shrinking of semiconductor process technology, it is imperative for foundries to identify design systematics at the early stages of the product lifecycle. As a result, the complex interactions between the design and manufacturing process, as well as the ability for critical pattern yield analysis, become more and more important [1, 2]. Design for Manufacturability (DFM) brings silicon manufacturing variability awareness on design configurations to address yield limitations using various techniques such as DFM rule checking and fixing guide, silicon validation (Sival) deck monitoring, machine learning enabled design rule checking (ML-DRC) and auto fixing, etc. The demand to identify and predict potential silicon fails has become unprecedentedly high as technology node advances, however, through all existing industry and commercial offerings, it is extremely hard to rank and intelligently determine which defects should be fixed with priority in order to efficiently speed up yield improvement. In this paper, we proposed an efficient analysis workflow to identify, rank design weakness based on silicon data, and provide guidance of confidence for yield-loss mitigation. The implementation is made possible by large scale data analytics using silicon-design correlations, which further provides a quick yield impact assessment shortly after tape-out. With this, a faster yield ramp becomes possible.