Gate Drive Optimization Framework with Electro-thermal Model of GaN HEMTs for High-Frequency DC-DC Converters

The gate drive circuitry design of Gallium Nitride High Electron Mobility Transistors (GaN HEMTs) is critical to power converter efficiency. The high switching frequency achievable by GaN means the gate drive circuitry must be designed to minimize parasitic inductance to prevent voltage overshoot. Additionally, the output current and characteristic capacitance of GaN transistors is dependent of the temperature of the device. This paper presents a framework utilizing an electro-thermal model for GaN devices to mitigate the benchtop tuning requirement of the gate drive resistors. The proposed electro-thermal model utilizes a Cauer approach in the equivalent circuit of a GaN switch. This adaptively changes the characteristics of the device, allowing for more accurate modeling in the design stage. The electro-thermal model is incorporated into a half-bridge model to simulate both the gate drive resistors as well as the parasitic inductances typical in a PCB design. With the full model, an optimization procedure is developed to find a Pareto efficient converter based upon desired switching frequency and bus voltage. Finally, the combined complete simulation and hardware experimentation are shown using a GaN half-bridge converter board operating as boost DC-DC converter for photovoltaic applications.