Memory Efficient Hash-Based Longest Prefix Matching Architecture With Zero False +ve and Nearly Zero False −ve Rate for IP Processing

A novel hash-based hardware architecture for longest prefix match (LPM) scheme has been presented for IP processing. The main idea is to have zero false positive (+ve) rate with negligible false negative (−ve) rate. This has been achieved by implementing hardware-based simple hash functions for faster generation of routing table addresses. Prefix table has been designed using multiple read-port memory modules to deploy concurrent access of multiple memory words. Moreover, in this architecture, memory requirement has been reduced by maintaining next-hop address pointers instead of keeping actual next-hop address using global next-hop address memory. Prefix search time is fixed and restricts an LPM search operation within a single clock cycle irrespective of IPv4 and IPv6 address suits. This architecture can accommodate increased prefix growth trend of 40–100 percent with unchanged memory capacity. After rigorous testing, false -ve rate is found mostly zero and reasonably negligible (
$\approx$
0.00512 percent) in worst-cases, however, false +ve rate is always zero. Lower bounds in memory requirements for four schemes of the proposed LPM architecture with their probable failure-rates are analysed. System failure-rates are observed against incremental prefix growth with variable number of hash functions ranging from 6 to 8 to ensure future sustainability of the scheme.