Design of Low Phase Noise VCO Considering C/L Ratio of LC Resonator in 0.18-μm CMOS Technology

A voltage-controlled oscillator (VCO) is usually designed by maximizing the quality (Q-) factor of the LC-tank resonator to realize a low phase noise. For the same frequency, the ratio of C/L affects the loaded Q-factor (
$\text{Q}_{\mathrm{ L}}$
) and then phase noise of the VCO. This affect has not been considered so far in the design of VCO because the conventional on-chip spiral inductor cannot be optimized for C/L ratio. This brief first investigates the effects of C/L ratio on the phase noise, and a design methodology for optimized C/L ratio using defected ground structure (DGS) resonator is presented. Then, the resonators were further evaluated based on Lg
_L
-product simulation for a fixed
$\text{I}_{\mathrm{ bias}}$
. Employing the proposed resonator, a very low phase noise
$\text{K}_{\mathrm{ U}}$
-band VCO is designed and implemented in 0.18-
$\mu \text{m}$
CMOS technology. The measurement result shows that the proposed VCO has a phase noise of −110.77 dBc/Hz at 1 MHz offset of 17.5 GHz carrier frequency and a frequency tuning range of 8.7%. The VCO consumes 2.3 mW power, which results in a figure of merit (FoM) of −191.95 dB.