An Error Resilient Design Platform for Aggressively Reducing Power, Area and Routing Congestion

In the traditional implementation methodology, a range of target voltage levels as defined in the Unified Power Format (UPF) together with the regular timing constraints are applied during the timing, area and power optimization stages of RTL-to-gate mapping. However, this approach usually requires stronger-driving-strength and bigger-size combinational and sequential standard cell mapping for maintaining the degraded performance caused by lower supply voltage. In this paper, an innovative power-saving design platform, using an analysis flow that effectively integrates the following methodologies, was proposed: (1) path retiming, slack redistribution, and modified razor insertions; (2) customized vector-free approaches and the automation procedures of generating corresponding and randomized stimulus for early-stage static and dynamic voltage-aware power analysis; and (3) precise prediction via Design Dependent Critical Path Monitor (DDCPM) for avoiding the happening of unexpected timing violations caused by the aggressive scaling of supply voltage during the fine-grained DVFS. Accordingly, not only dramatic reductions of power consumption and chip area but the serious routing congestion issues often happened in a design with high occupation of long-depth critical timing paths could also be effectively alleviated. One of our experimental results in TSMC 55nm process node shows the maximum power and area reduction is 62.7% and 29.1%, respectively.