Architecture design and hardware implementation of AES encryption algorithm

With the rapid development of the information society, network information security has attracted more attention. Traditional software encryption technology is becoming more and more difficult to ensure people's information security. How to quickly and efficiently ensure people's information security has become one of the key projects studied by scholars. Under this background, this paper designs a simple advanced encryption standard AES FPGA hardware implementation. The content includes the hardware structure design of AES encryption algorithm, comprehensive wiring with Quartus II 13.0, and simulation verification on Modelsim se 10.5.