Nanosheet FETs and their Potential for Enabling Continued Moore's Law Scaling

We report on nanosheet (NS) FETs as promising candidates to replace finFETs and continue delivering profitable node to node scaling gains. Key fabrication challenges addressed here include device parasitics' reduction via inner spacers integration and channels' stress control. Further scaling options may involve evolution into a forksheet (FS) type of configuration with shrunk p-n spacing, and/or stacking of different polarity devices into a single 3D structure. Lastly, by fully exploring the third dimension, vertical NS (VNS) FETs are also considered for applications such as the selector of ultra-scaled MRAM cells.