Stress adjusting for hillock size reduction in UTS CIS base on graphics analysis

The hillock on top metal (Cu wire) of logic wafer will cause Cu diffuse and lead to interconnect failure in the UTS CIS device manufacturing. A graphics analysis method was used to study the hillock size and density affected by the film thermal stress relaxation on different wide Cu wires. We innovatively reduced the hillock size through stress adjusting of Cap film Si(C)N and got good Cu diffuse improvement in TSV process.