A Comparative Analysis of Fault Tolerance Methods in 3D-NoC

Networks-on-Chips (NoCs) have found wide acceptance in many-core systems for on-chip communication due to their ease in addressing communication problems in integrated systems. Due to the incompetence of the 2D NoC structures, academia and industry have moved towards the 3D-NoC. The 3D-NoC can be manufactured with the help of Through Silicon Vias (TSV) as an interconnecting mechanism between the horizontal layers. These TSV links exhibit high vulnerability to the faults in the system. Significant research has been done to reduce this vulnerability by employing a few algorithms and schemes. This paper provides a survey of the different methods applied and their further advancements.